This invention relates generally to an isolation process for semiconductor devices, and more specifically to an improved LOCOS isolation process using a framed oxidation mask and a polycrystalline silicon (polysilicon) buffer in the manufacture of semiconductor devices.
In the manufacture of semiconductor devices, typically thousands of individual transistor devices are formed upon a single silicon substrate. These devices are interconnected to form complex circuits, also known as integrated circuits, as required for a particular circuit design. Because the transistors are formed within the same substrate, the transistors must be electrically isolated except as interconnected according to the circuit design; otherwise, undesired electrical connections between the transistors would cause circuit shorts. Several methods exist for device isolation and vary with the type of device being manufactured. One device isolation method widely used in the manufacture of insulated gate field effect transistors (IGFETs) is the well-known local oxidation of silicon, or LOCOS, process.
In a typical LOCOS process a thin silicon oxide layer, or pad oxide, is grown over a silicon substrate, and then a silicon nitride layer is deposited over the silicon oxide layer. Next, the pad oxide and nitride layers are patterned by known lithographic techniques to partially expose the substrate. The exposed regions of the substrate are known as the field regions. Regions of the substrate still covered with the pad oxide and nitride are known as the active regions and will eventually contain the transistors for the integrated circuit. A thick silicon oxide insulator, or field oxide, is grown in the field regions of the silicon substrate by placing the substrate in a steam ambient, typically at a temperature in the range of 900.degree.-1100.degree. C., for an extended time. The steam reacts with the exposed silicon to form silicon oxide. The thick field oxide provides electrical isolation by increasing the threshold voltage in the field region, thereby preventing the formation of a conductive path in the surface of the underlying silicon substrate. The active regions remain unoxidized and covered by nitride during the field oxide growth. Finally, the nitride and pad oxide are removed. Transistors are then formed by additional processing in the active region.
The continuing trend in integrated circuit design is to further increase the packing density of transistor devices on the silicon substrate. This is important for increasing both transistor performance and the quantity of the devices that can be placed upon a given surface area of silicon. The need for increased device density is most crucial in the manufacture of memory circuits, especially random access memories (RAMs), because of the use of large memory arrays formed by the replication of tightly-packed groups of devices. Device density, and hence memory density, can be increased by shrinking all or some of the dimensions of the these tightly-packed device groups. One approach for increasing the packing density is the reduction of the lateral separation used between devices for electrical isolation. Even with the device sizes unchanged, for example devices having constant effective widths, a reduction in the device separation distance can significantly increase the packing density on an integrated circuit.
However, there are several limitations to the reduction of the device isolation distance. In the conventional LOCOS process, lateral oxidation between the oxidation mask and the substrate results in a tapering of the grown field oxide at the active region boundaries which is known as a bird's beak. This bird's beak partially penetrates into the active region of the substrate and reduces the size of the devices that can be formed in the active region. This penetration is also known as field encroachment. That portion of the field oxide thinned by the formation of the bird's beak does not provide adequate device isolation. Furthermore, the length of the bird's beak sets a minimum limit on the degree to which the device isolation distance, or field separation, can be decreased. Indeed, conventional LOCOS is not even viable for current sub-micron memories because of its excessive bird's beak length.
One approach used to reduce the bird's beak length is the known polysilicon-buffered LOCOS, or PBL, process in which a polysilicon buffer layer is deposited between the pad oxide and nitride of the conventional LOCOS process. Since it is known that oxygen diffusion through the pad oxide to the silicon substrate is a major contributor to bird's beak formation, the addition of the polysilicon buffer layer reduces the lateral field encroachment by reducing the degree of oxygen diffusion through the pad oxide.
Another limitation on the reduction of field separation is the acceptable range of thicknesses for the nitride layer. Even though an increase in the nitride layer thickness reduces the bird's beak length due to increased nitride layer rigidity, the thicker nitride increases stress on the silicon substrate. It is desirable to minimize substrate stress to avoid creating disruptions in the substrate surface such as crystal dislocations which promote junction leakage and low junction breakdown voltage at the active region edges. A deposited nitride exhibits considerable tensile stress which is transferred to the substrate and can damage the substrate surface during field oxide growth.
Buffer layers between the nitride layer and the silicon substrate such as the pad oxide and the polysilicon buffer of the PBL process reduce, but do not eliminate, the effects of the nitride stress on the substrate. The choice of nitride thickness is a compromise between reducing bird's beak length and reducing substrate stress. An accepted guideline for an optimum compromise is the use of a three-to-one ratio of nitride thickness to the combined buffer thicknesses.
A further limitation on field separation reduction is the resolution limit of current optical lithography equipment. This limitation is most acute in the manufacture of sub-micron devices. When attempting to reduce the field separation below one-half of a micron, as in current high-density RAM manufacture, it is impossible to define the field region by lithography because the lithography equipment's lower resolution limit is greater than the desired field separation.
To overcome this lithography limitation, sidewalls are added to the edges of the patterned nitride and buffer layers (adding sidewalls is also known as framing the nitride mask). These sidewalls are formed by depositing a second nitride layer over the patterned first nitride layer. The second nitride layer is then etched anisotropically to form sidewalls. Because the sidewalls are formed without the use of a patterned mask, the field separation can be reduced below the resolution limits of optical lithography. Another advantage of the sidewalls is the prevention of oxygen diffusion into the edges of the pad oxide or other buffer layers which reduces bird's beak formation.
A problem with this sidewall formation method, however, is poor sidewall uniformity. The height of the first nitride layer's top surface determines the etched sidewall's dimensions, such as height and width at the sidewall base. Yet, because some of the first nitride layer is removed during the sidewall etching, it is difficult to maintain uniformity in the sidewall dimensions. Also, the control of the etching is difficult since the first nitride and second nitride layers have essentially the same etch selectivities.
In another sidewall formation method a low temperature oxide (LTO) layer is deposited onto the first nitride layer. Both the first nitride and LTO layers are etched to be self-aligned. In this method the height of the LTO layer's top surface determines the etched sidewall's dimensions. Since the LTO and nitride layers have similar etch selectivities, some of the LTO layer is removed during sidewall formation, and as in the previous method, sidewall uniformity is difficult to achieve. Additionally, the deposited LTO layer is non-uniform which further contributes to poor sidewall dimension uniformity.
In both of the above sidewall formation methods, the steam used during field oxide growth can attack pinholes or small cracks in the first nitride layer and form ammonia. This ammonia can diffuse to the silicon substrate surface and react to form silicon nitride spots. These nitride spots are removed in later processing steps, but small holes can remain in the substrate surface at the former nitride spot locations. These holes, if formed, contribute to poor gate oxide quality in finished devices. Because the first nitride layer is uncovered during field oxide growth, both of the previous sidewall formation methods suffer from this detrimental process known as the Kooi effect.
In the first method, the second nitride layer on top of the first nitride layer is completely etched away exposing the top of the first nitride layer. In the second method the LTO is removed before the field oxide is grown, also exposing the top of the first nitride layer. The LTO is not removed following field oxide growth because the field oxide would be thinned excessively resulting in poor device isolation.
Accordingly, a need existed for a LOCOS isolation process for forming sidewalls providing independent control of the sidewall dimensions, more uniform sidewall etch control, and prevention of damage from the Kooi effect.
It is therefore an object of this invention to provide an improved method for LOCOS isolation.
It is a further object of this invention to provide an improved method for LOCOS isolation which provides more uniform sidewall etch control.
It is still a further object of this invention to provide an improved method for LOCOS isolation that uses conventional processing steps.
Still another object of this invention is to provide an improved method for LOCOS isolation that prevents damage due to the Kooi effect.
A still further object of this invention is to provide an improved method for LOCOS isolation that allows adjustment of the sidewall dimensions independently of the thicknesses of the first nitride layer and underlying buffer layers.